Design Engineer

Design engineer responsible for SerDes frontend design and Firmware development

At Chronos I lead the development of the circuits of the core technology and the methodology and design flow to implement, debug and test it using standard EDA. I worked to model and implement the software infrastructure to deploy Chronos, using Python and TCL, and created mathematical models and analysis tools to explore the design space. Besides that, I worked writing patents, white papers and technical reports.



Technical Director

While teaching at PUCRS, I was responsible for the following undergraduate courses for Computer Engineering and Computer Science: Computer Architecture; Computer Organization; Basic Software Programming; and Peripheral Programming. In these courses I relied on the usage of electronic design automation tools from Cadence, Mentor and Synopsys for design, simulation, synthesis and verification of integrated circuits. I also relied on the usage of instruction set simulators and debugging tools. Programming classes included using C/C++ and Python.

At PUCRS I advised the work of more than 10 undergraduate students and 2 graduate students pursuing their M.Sc. degrees. I was also responsible for starting a partnership with Stefanini to create a laboratory to launch new startup companies in Brazil.


Assistant Professor

During my work as a research fellow at PUCRS I worked in 4 main projects:

1 - I led the development of cell libraries for asynchronous circuits targeting the following technologies from ST: 65nm Bulk CMOS and 28nm FD-SOI. My library design tasks included layout design (Virtuoso), analog simulation (Spectre), parasitics extraction (Calibre), metastability analysis (MetaACE) and models generation (ELC, Abstract Editor and Verilog design).

2 - I led the development of a new asynchronous circuit template targeting robustness against PVT variations. I worked with different data encodings, handshake protocols and asynchronous circuits templates. I created a novel encoding and protocol solutions and was the lead designer of our new asynchronous circuit template. I also worked on a design flow for automating the process of synthesis, optimization and verification of circuits targeting the template.

3 - I was part of the team that developed and optimized several different asynchronous NoC routers, including Hermes-GLP and Hermes-AA. My tasks included design (using VHDL and Verilog), digital simulation (Incisive), synthesis (RTL Compiler) and performance and power estimation and optimization (Encounter). I also worked on architectural level, exploring NoC architectures and topologies for optimizing our routers and different bus architectures for easing SoC interconnection. The designs targeted the following technologies: XFAB 350nm, ST 65nm, IBM 130nm and TSMC 180nm.

4 - I was responsible for leading the backend team in the design of a microcontroller-based SoC targeting TSMC 180nm. I managed the team and performed practical activities on synthesis and layout generation (using RTL Compiler, Encounter and Virtuoso). I was also involved in the architectural design and analysis of the next generation of our microcontroller, being responsible for exploring different bus architectures and integrating them in the system-on-chip design.


Research Fellow

I was responsible for working on the development of the cell libraries required by a new asynchronous circuits template called Blade. My tasks included research and hands-on work. For the latter, I was responsible for modeling and analyzing performance, power and robustness figures of asynchronous circuits, at the cell level, and optimizing them. For that, I used tools from Mentor, Cadence and Synopsys, including: Virtuoso for layout design; Calibre for extraction; HSPICE and Spectre for analog simulation; and ELC for library characterization. I also worked on the development of methods to analyze the susceptibility of our cells to hazards and charge sharing effects, as well as to metastability effects. The cell libraries were designed in the 28nm FD-SOI and the 65nm Bulk CMOS Design Kits from STMicroelectronics.

Besides my tasks on library optimization, I was also involved in the development of an automation design flow for circuits based on the Blade template and in a method for modeling and analyzing performance figures. The design flow was done using TCL and targeted the Synopsys Implementation Framework (Design Compiler and IC Compiler). My work with the Blade template required exploration of its unique handshake protocol and different data encodings, used in different parts of the circuit. Also, part of my tasks required using Petrify and 3D, classic asynchronous circuits synthesis tools.

Visiting Scholar

At UNISC I was responsible for teaching Computer Engineering and Computer Science undergraduate students in the following courses: Computer Architecture; Microelectronics. For the former, I used VHDL for describing a MIPS processor from scratch, to explore architectural subjects, and Mentor's Modelsim to simulate the design. For the Microelectronics course, I relied on the Cadence Framework to teach students all concepts from full-custom design to top-level integration. In the course we used tools for analog and digital simulation, layout design, parasitic extraction, electrical characterization, timing analysis, logic synthesis and place and route. Programming classes included using C/C++ and Python.

I was responsible for gathering requirements from different departments of the company and configuring internal software and database infrastructure to meet their needs. I worked with the Oracle Framework and created reports and documentation using data obtained through SQL queries.

Personal details

Matheus M.

Summary

Technical skills

Work Experience