Personal details
Juan I.
Timezone: Buenos Aires (UTC-3)
Summary
I am an electronic engineer with a lot of experience in VHDL and C programming. My expertise is the digital signal processing focused in digital communications.
Work Experience
Electronic Engineer
VENG SA | Jul 2015 - Present
Impact
FPGA
Vivado
Ise
R & D engineering. Electronic, VHDL, C, Matlab.
Personal Projects
Flight Termination Receiver
2017
VHDL (VHSIC Hardware Description Language)
Development of the digital signal proccessing stage of a flight termination receiver (PCM/FM receiver).