Image / Video Processing on FPGA, Front End Design, VHDL, Verilog, Synthesis, Simulation, PnR & Timing analysis, System Generator, Hardware Co Simulation, Hardware in Loop, Fixed Point Implementation, Xilinx FPGA, RTL Development, Xilinx & Lattice EDA Tools, MATLAB, Simulink, HDL Coder, VHDL Code Generation, Computer Vision, Machine Learning, Xilinx Spartan, Virtex, Zynq SoC, Lattice MachXO3

• Experience in VLSI design / RTL design with VHDL, Verilog 
• Hands-on experience in Xilinx, Lattice, MATLAB, Mentor Graphics EDA tools
• Real time testing of FPGAs using MATLAB hardware co simulation (System Generator) & Hardware in Loop (HDL Coder)
• Experience of using real time debug tools such as ChipScope
• Experience of multiple clock domains
• Experience in Synthesis, Place & Route, Optimization and Debugging
• Experience with MATLAB, Simulink, HDL Coder, HDL Verifier, Image/Video/Signal Processing, Computer Vision toolboxes

• Design Image/Video/Signal Processing algorithms, efficient implementation on FPGA
• Image enhancement, Edge-detection algorithms, Contrast Enhancement, Image Scaling, Adaptive Median Filter, RGB2YCbCr, RGB2HSV, Bilateral Filter, High Dynamic Range Extension, Tonemap, Color Correction, Image Sharpening, VGA Controller, 
• Real Time Camera Based Applications (HDR/ Panorama/ Image Stitching or Various Effect)
• Stereo Image/ 3D Image based applications
• Fixed point implementation: CORDIC (Square-root, Divider, TAN Inverse)

Personal details

Jigarkumar M.

Summary

Technical skills