System IP Hardware Modeling Engineer

Numem Design Verification Engineer Job Opportunity:

The Numem Team is seeking experienced Functional Verification DV Engineers who are driven by a passion for learning and excellence.

• Develop and maintain system IP hardware

• Develop and maintain SystemC functional and cycle accurate transaction level (TLM) models

• Develop performance and power monitors and metrics

• Develop SystemC based simulation environment for performance analysis

• Conduct system level resource trade-off analysis

• Support development of RTL and FPGA hardware implementation

• Bachelor’s, or Master’s in Electrical Engineering, Computer Engineering, or a related field.

• 5+ years of experience in C++, SystemC/TLM2.0 modeling for hardware architectures.

• Strong knowledge of computer architecture, SoC design, and hardware-software interaction.

• Proficiency in C++ programming and SystemC modeling techniques.

• Experience with performance modeling, cache coherency, and memory subsystem analysis.

• Familiarity with hardware simulation tools, virtual platforms, and hybrid emulation environments.

• Hands-on experience with embedded systems, firmware, and device driver development.

• Strong debugging and profiling skills for hardware/software interaction.

Education/Location/Requirements

• BS in EE/CE/CS (or equivalent) required; MS preferred (not required).
• Location preferably in Phoenix area or Silicon Valley or other locations in USA
• US Citizen or Permanent Resident Only

Job Type: Full-time

Pay: $170,000.00 - $200,000.00 per year

Benefits:

• 401(k)
• Dental insurance
• Health insurance
• Paid time off
• Vision insurance

Work Location: Remote