Design Verification Engineer

Senior Design Verification Engineer

We are looking for design verification engineers with 5 to 10 years of experience, Multiple positions are available (Remote or Onsite)

Key Responsibilities

• 5 or more years of proven verification experience in a hardware development setting
• Strong background in System Verilog and UVM verification methodologies
• Strong debug skills and experience with debug tools such as DVE/Verdi
• Proficiency in Object Oriented programming, computer architecture, and data structures
• Develop/Maintain tests for functional verification and performance verification at the core level
• Build testbench components to support the next-generation IP
• Maintain or improve current test libraries to support IP-level testing
• Create hardware emulation build to verify the IP functional performance
• Maintain and improve the current hardware emulation environment to speed up the runtime performance and improve the debug facility
• Provide technical support to other teams

Preferred Experience

• Good at C/C++
• Familiarity with System Verilog and modern verification libraries like UVM
• Experience/Background on Computing/Graphics is a benefit

Education

Bachelor or Master's in Electrical Engineering, Computer Engineering, or Computer Science

Job Type: Full-time

Pay: $180,000.00 - $195,000.00 per year

Schedule:

• Day shift

Experience:

• SystemVerilog: 5 years (Required)

Willingness to travel:

• 25% (Preferred)

Work Location: Remote