We are seeking skilled and motivated individuals to join our FPGA development team. The successful candidate will be responsible for the design, implementation, verification, and testing of FPGA-based digital systems used in cutting-edge networking products. You will collaborate with cross-functional teams including hardware, software, and customer engineering to develop quality, innovative and reliable solutions, which are deployed in an extremely diverse range of industries.

What You’ll Do

Design and implement digital logic using VHDL for FPGAs.
Develop and optimise high-speed, low-latency FPGA designs targeting AMD/Xilinx Ultrascale Plus devices.
Integrate FPGA modules with embedded systems, processors, and high-speed interfaces (e.g., PCIe, Ethernet, HBM, DDR4, AXI)
Perform functional simulation, synthesis, place-and-route, timing analysis, and optimization using industry-standard EDA tools (e.g. Vivado, ModelSim).
Leverage industry-standard development tools and workflows to manage work, code changes, testing and integration (e.g. Jira, Git, CI/CD).
Create and maintain both internal and customer facing documentation including design specifications, test plans, and user guides.
Work closely with hardware, software and account teams to define technical requirements and business needs.
Support platform bring-up, validation, and debugging in the lab using test equipment such as oscilloscopes, logic analyzers, and JTAG tools.
Contribute to continuous improvement of FPGA development processes, methodologies and design practices.

Qualifications

Required:

Bachelor’s or higher degree in Electrical Engineering, Computer Engineering, or related field.
5+ years of experience in FPGA or ASIC design and development.
Proficiency in a hardware description language (HDL) such as VHDL or Verilog.
Experience with FPGA development tools (Vivado, Quartus, etc.).
Strong understanding of digital logic, high-speed design, and timing closure.
Candidates must be based in Poland.
Please clearly state your current work authorization status in your application.

Preferred: